RTL設計スタイルガイド Verilog HDL編(System Verilog対応版,HDL設計入門 改訂版: VHDL、Verilog-HDL、合成を用いた設計,Model Design for AXI4 Master Interface Generation,Integrating a VHDL Design into a Peripheral - FPGA Developer,Integrating a VHDL Design into a Peripheral - FPGA Developer